1. Field of the Invention
The present invention relates to a wafer connection technology, particularly to a submicron connection layer and a method for using the same to connect wafers.
2. Description of the Related Art
The academia and industry have regarded the prominent 3D IC as the main measure to continue the Moore's law. TSV (Through Silicon Via) is a vertical metal interconnection to implement the high speed information transmission between the upper and lower elements inside a chip and has been a trend to fabricate chips. Wafer bonding is a critical step to integrate 3D IC, wherein wafers are aligned and bonded to each other, and wherein TSV realizes the layer-to-layer interconnections thereof. Many wafer bonding technologies are derived from the MEMS (microelectromechanical system) technology and the conventional package technology. However, a 3D IC wafer bonding platform is 5-10 times more precise than that of the MEMS or 3D integration technology. The alignment precision of final 3D IC products may reach the micron or even submicron scale.
The wafer bonding technology includes the silicon direct bonding methods, the metal-metal bonding methods, and the polymer adhesive bonding methods. The metal eutectic bonding method is one of the metal-metal boding methods, for example, the Cu—Sn eutectic bonding method. In the conventional Cu—Sn eutectic bonding method, the physics of the intermetallic compound would constrain the thickness of the connection layer to be in the scale of 3 μm. Besides, the roughened surface of the Cu—Sn intermetallic compound (IMC) degrades reliability of bonding.
Accordingly, the present invention proposes a novel submicron connection layer and a method for using the same to connect wafers in order to overcome the abovementioned problems.